История изменений
Исправление devl547, (текущая версия) :
если «четвертинка» сможет самостоятельно выполнять инструкцию - какие проблемы?
The FPU can receive up to four ops per cycle. These ops can only be from one thread, but the
thread may change every cycle. Once received by the FPU, ops from multiple threads can be executed.
A 128-bit integer multiply accumulate (IMAC) unit is incorporated into FPU pipe 0. The IMAC performs integer fused multiply and accumulate, and similar arithmetic operations on AVX, MMX and SSE data. A crossbar (XBAR) unit is integrated into FPU pipe 1 to execute the permute instruction along with shifts, packs/unpacks and shuffles. There is an FPU load-store unit which supports up to two 128-bit loads and one 128-bit store per cycle.
Грубо говоря - у тебя одно ядро может загрузить FPU работой и всё, приехали.
Исправление devl547, :
если «четвертинка» сможет самостоятельно выполнять инструкцию - какие проблемы?
The FPU can receive up to four ops per cycle. These ops can only be from one thread, but the
thread may change every cycle. Once received by the FPU, ops from multiple threads can be executed.
A 128-bit integer multiply accumulate (IMAC) unit is incorporated into FPU pipe 0. The IMAC performs integer fused multiply and accumulate, and similar arithmetic operations on AVX, MMX and SSE data. A crossbar (XBAR) unit is integrated into FPU pipe 1 to execute the permute instruction along with shifts, packs/unpacks and shuffles. There is an FPU load-store unit which supports up to two 128-bit loads and one 128-bit store per cycle.
Грубьо говоря - у тебя одно ядро может загрузить FPU работой и всё, приехали.
Исправление devl547, :
если «четвертинка» сможет самостоятельно выполнять инструкцию - какие проблемы?
The FPU can receive up to four ops per cycle. These ops can only be from one thread, but the
thread may change every cycle. Once received by the FPU, ops from multiple threads can be executed.
A 128-bit integer multiply accumulate (IMAC) unit is incorporated into FPU pipe 0. The IMAC performs integer fused multiply and accumulate, and similar arithmetic operations on AVX, MMX and SSE data. A crossbar (XBAR) unit is integrated into FPU pipe 1 to execute the permute instruction along with shifts, packs/unpacks and shuffles. There is an FPU load-store unit which supports up to two 128-bit loads and one 128-bit store per cycle.
Исходная версия devl547, :
если «четвертинка» сможет самостоятельно выполнять инструкцию - какие проблемы?
The FPU can receive up to four ops per cycle. These ops can only be from one thread, but the
thread may change every cycle. Once received by the FPU, ops from multiple threads can be
executed.