Продолжение анонса MIPS Open
https://wavecomp.ai/wave-computing-adds-mips32-microaptiv-cores-to-mips-open-...
Wave Computing Adds MIPS32 microAptiv Cores to MIPS Open Program
CAMPBELL, Calif., May 13, 2019– Wave Computing,® Inc., the Silicon Valley company accelerating artificial intelligence (AI) from the datacenter to the edge, today announced it will include the MIPS32® microAptiv™ cores in the newest release of MIPS Open program components. One of the smallest and low power CPUs in the MIPS product line, the MIPS32 microAptiv core is a highly-efficient, compact, real-time solution for microcontrollers (MCU) and entry-level embedded market applications such as automotive, Internet of Things (IoT) and home networking appliances. The Verilog register transfer level (RTL) code for the MIPS32 microAptiv cores and other MIPS Open program components are available for immediate download at http://www.mipsopen.com/resources/download.
“When the MIPS32 microAptiv core was introduced, it delivered much higher clock speeds than other MCU cores as well as better code density,” said Linley Gwennap, principal analyst of The Linley Group. “Now that Wave Computing is offering microAptiv in the MIPS Open components, SoC designers are free to integrate this reliable and powerful CPU without any license fees or royalties. This announcement marks a significant advance for the MIPS Open initiative.”
[...]
The new set of MIPS Open program components will include two different versions of the microAptiv Verilog RTL code:
- microAptiv MCU core – designed with application-specific features and real-time performance for microcontroller SoC development.
- microAptiv MPU core – includes a cache controller and MMU facilitating embedded system designs executing operating systems such as Linux.
In addition to the Verilog RTL code, the package also includes documentation, configuration tools and a verification suite.
...
Хотите создать собственный микроконтроллер с необычными параметрами, например добавленными вами инструкциями, и конкурировать с PIC32, STM32 или AVR? Или просто использовать такой проект для трудоустройства?
С сегодняшнего дня вы можете скачать свободно конфигурируемое ядро MIPS microAptiv UP, совместить его с MIPSfpga+ и запустить на ПЛИС, или спроектировать с ним ASIC и выпустить на фабрике - например тайваньской TSMC или GlobalFoundry в Дрездене (российские Микрон, Анстрем и Ангстрем-Т под санкциями).
Это ядро использовал Microchip Technology, Broadcom, Samsung и многие другие компании.
В опции конфигурации входит например несколько наборов регистров (можно сделать скажем 16 наборов по 32 регистра с автоматическим переключением наборов по прерыванию, без сохранения контекста в память), расширение для DSP, ScratchPad RAM (блок памяти с латентностью кэша, который можно также использовать не как память, а как блок ввода-вывода скажем сетевых пакетов или даже математический сопроцессор), два интерфейса для сопроцессоров (CorExtend и Cop2), конфигурируемый размер и количество секций кэша.
Последнее полезно для студенческой дипломной работы: исследование как параметры кэша влияют на производительность процессора на тех или иных алгоритмах с той или иной латентностью памяти.
Кроме MIPS microAptiv UP выложен также MIPS microAptiv UC - более малое ядро без кэшей, с предсказуемой латентностью обращения к памяти через SRAM-like протокол. Здесь тоже материал для студенческой дипломной работы - сделать для него обвязку, как MIPSfpga+ является обвязкой для MIPS microAptiv UP ( https://github.com/MIPSfpga/mipsfpga-plus ). Имея в резюме такую работу, можно устроиться не только в Wave и Microchip Technology, но и в ARM, Intel, Apple, AMD, ST Microelectronics, Texas Instruments. И в российские компании - Байкал, ЭЛВИС и другие.
Еще можно делать дипломные работы, создавая среды верификации компонент MIPS microAptiv UC/UP (TLB MMU, кэшей, DSP unit, DSPRAM, всего ядра) на SystemVerilog, UVM, Portable Stimulus. С последним еще проще трудоустроиться.
Вот еще основа для дипломной работы - сравнение производительности алгоритмов DSP на процессоре с DSP расширением против процессора без DSP расширения, с учетом цены расширения (статического и динамического энергопотребления, размеров ядра) https://s3-eu-west-1.amazonaws.com/…/MD00928-2B-mAptiv-APP-…
Теперь вы можете скачать свободно конфигурируемое ядро MIPS microAptiv UP, совместить его с MIPSfpga+ и запустить на ПЛИС, или сделать с ним ASIC и выпустить микросхему на фабрике. Конкурировать с Microchip PIC32MZ или Microchip PIC32MM. Или просто использовать такой проект для трудоустройства.
В опции конфигурации входит например несколько наборов регистров (можно сделать скажем 16 наборов по 32 регистра с автоматическим переключением наборов по прерыванию, без сохранения контекста в память), расширение для DSP, ScratchPad RAM (блок памяти с латентностью кэша, который можно также использовать не как память, а как блок ввода-вывода скажем сетевых пакетов или даже математический сопроцессор), два интерфейса для сопроцессоров (CorExtend и Cop2), конфигурируемый размер и количество секций кэша.
Последнее полезно для студенческой дипломной работы: исследование как параметры кэша влияют на производительность процессора на тех или иных алгоритмах с той или иной латентностью памяти.
Кроме MIPS microAptiv UP выложен также MIPS microAptiv UC - более малое ядро без кэшей, с предсказуемой латентностью обращения к памяти через SRAM-like протокол. Здесь тоже материал для студенческой дипломной работы - сделать для него обвязку, как MIPSfpga+ является обвязкой для MIPS microAptiv UP ( https://github.com/MIPSfpga/mipsfpga-plus ). Имея в резюме такую работу, можно устроиться не только в Wave и Microchip Technology, но и в ARM, Intel, Apple, AMD, ST Microelectronics, Texas Instruments. И в российские компании - Байкал, ЭЛВИС и другие.
Еще можно делать дипломные работы, создавая среды верификации компонент MIPS microAptiv UC/UP (TLB MMU, кэшей, DSP unit, DSPRAM, всего ядра) на SystemVerilog, UVM, Portable Stimulus. С последним еще проще трудоустроиться.
Вот еще основа для дипломной работы - сравнение производительности алгоритмов DSP на процессоре с DSP расширением против процессора без DSP расширения, с учетом цены расширения (статического и динамического энергопотребления, размеров ядра) https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00928-2B-mAptiv...
Качать здесь: https://www.mipsopen.com/resources/download/
Лицензия:
MIPS Open™ Core License Agreement ver 1.0 For the microAptiv UP/UC Core (“MIPS Open Core”)
© 2019 MIPS Tech, LLC
THIS MIPS OPEN™ CORE LICENSE AGREEMENT FOR THE microAptiv UP/UC CORE (“AGREEMENT”) CONSTITUTES A BINDING CONTRACT ON YOU AND GOVERNS YOUR USE OF THE MIPS OPEN CORE DELIVERABLES. By clicking “Accept” to this Agreement below, the person or entity so accepting (“You”) agree to be bound by this Agreement. If You are entering into this Agreement on behalf of a company, organization or other legal entity (an “Entity”), You are agreeing to this Agreement on behalf of that Entity and are representing to MIPS that You have the authority to bind such Entity to this Agreement, in which case the terms “You,” “Your” or a related capitalized term herein shall refer to such Entity. If You do not have such authority, or if You do not agree with this Agreement, You must not accept this Agreement and You do not have a license to use the MIPS Open Core. An Entity does not include its subsidiaries or affiliates. Each and every subsidiary or affiliate of such Entity must separately execute this Agreement in order to have access to and use the MIPS Open Core.
The purpose of this Agreement is to establish the terms and conditions under which You may use and access the MIPS Open Core Deliverables as described herein and provided by MIPS Tech, LLC, a Delaware limited liability company (“MIPS”). This “Agreement” refers to this Agreement licensing the MIPS Open Core identified at the top of page 1 hereof and is not a license agreement for the “MIPS Open Architecture” as defined and used in the separate MIPS Open agreement for its license (the “MIPS Open Architecture Agreement”) nor an agreement licensing another core under a MIPS Open program.
1. Definitions:
(a) “Authorized Foundry” means a foundry approved by MIPS under this Agreement for You to have manufactured a semiconductor product incorporating a MIPS Open CERTIFIED Independent Core Implementation, made in accordance with applicable law and for an end use and end user(s) in compliance with U.S. export laws and regulations, such approval to be updated by MIPS from time to time.
(b) “MIPS Direct-Licensed Core” means any microprocessor core (other than the MIPS Open Core identified in this Agreement) that is made generally available for license from MIPS or its affiliates or predecessors that was either (i) licensed by MIPS or its affiliate or predecessor, to You or Your affiliate, or (ii) developed by You or Your affiliate under rights licensed under a MIPS Architecture by MIPS or its affiliate or predecessor.
(c) “MIPS Architecture” means the RISC technology processor instruction set architecture (“ISA”) or any application specific extension (“ASE”) to such architecture, and any associated privileged resource architecture (“PRA”) developed by or for MIPS or its predecessor entities.
(d) “MIPS Open Core IP Rights” means MIPS’ copyrights, patents, patent applications, and other intellectual property rights in the MIPS Open Core Deliverables delivered to You by MIPS (or a MIPS Open Core licensee of this Agreement in compliance with its license under this Agreement). “MIPS Open Core IP Rights” do not include copyrights, patents, patent applications or other intellectual property rights (i) that cover implementations of any MIPS Architecture or microprocessor core (including Direct-Licensed Cores and MIPS Open CERTIFIED Independent Core Implementations) except to the extent that such rights are necessary to implement the MIPS Open Core in accordance with this Agreement or (ii) that are owned or held by any affiliate or parent company of MIPS or any entity other than MIPS.
(e) “MIPS Open Core Deliverables” means deliverables for the MIPS Open Core or MIPS Open Tools made available by MIPS under this Agreement for You to download from the MIPS Open website upon Your acceptance of this Agreement, as updated from time to time, and includes without limitation MIPS Open Core Documentation.
(f) “MIPS Open Core Documentation” means the technical reference manuals for the MIPS Open Core.
(g) “MIPS Open Core Mark(s)” means the MIPS Open CERTIFIED™ mark and logo, and other marks and logos if designated by MIPS as applicable to a MIPS Open Core license.
(h) “MIPS Open CERTIFIED Independent Core Implementation” means an implementation of the MIPS Open Core in netlist format targeting a semiconductor manufacturing process for an Authorized Foundry, which (1) You developed independently and internally in compliance with this Agreement (a “MIPS Open Independent Core Implementation”), and (2) has been certified in writing as passing the compatibility verification process for the MIPS Open Core attached in Exhibit A hereto (“MIPS Open CERTIFIED”) by MIPS or a MIPS-designated third-party verification provider (each, a “MIPS Open Verification Partner”). A MIPS Open CERTIFIED Independent Core Implementation does not include any: (i) MIPS Open Independent Core Implementation that is not MIPS Open CERTIFIED or incorporated into a product manufactured at a foundry other than an Authorized Foundry, (ii) core implementation developed in whole or in part from a MIPS Direct-Licensed Core, or (iii) core implementation licensed or provided to You by a third party (unless such core implementation is a MIPS Open CERTIFIED Independent Core Implementation that You licensed from a MIPS Open licensee in accordance with this Agreement).
(i) “MIPS Open Tools” under this Agreement means the software, firmware, tools and documentation identified by MIPS as “MIPS Open” applicable for design and use with the MIPS Open Core, which are posted and accessible in digital form for authorized licensees which are made available by MIPS on MIPS’ designated website(s).
2. Verification: Before manufacturing or commercializing any core implementation of the MIPS Open Core licensed under this Agreement, You must ensure that any such core implementation is a MIPS Open CERTIFIED Independent Core Implementation (including if you have sublicensed such core implementation from another licensee of the MIPS Open Core). You must notify MIPS in writing of each MIPS Open CERTIFIED Independent Core Implementation within thirty (30) days of such verification by a MIPS Open Verification Partner. You agree to provide upon request by MIPS or its authorized MIPS Open Verification Partner, information demonstrating that such core implementation in its current format is a MIPS Open CERTIFIED Independent Core Implementation.
3. License:
(a) MIPS Open Core. Provided that You comply with the terms and conditions of this Agreement (including Section 2 (Verification) and Section 12 (MIPS Open Core Development Covenants)), MIPS hereby grants You a non-exclusive, worldwide, royalty-free, non-transferable (except as provided in Section 13) right and license (without rights of sublicense except as provided in subsection 3(a)(iii) below) solely under MIPS Open Core IP Rights, to:
(i) access and use the MIPS Open Core Deliverables internally to develop MIPS Open CERTIFIED Independent Core Implementations, verified by a MIPS Open Verification Partner, for incorporation into Your products or tools (or your authorized sublicensee’s products or tools under subsection (iii) below), provided that Your right to access and use the MIPS Open Tools is subject to subsection 3(b) below;
(ii) make, have made, use, sell, offer for sale and import the MIPS Open CERTIFIED Independent Core Implementations as incorporated in Your products at an Authorized Foundry(ies) to whose process the respective MIPS Open CERTIFIED Independent Core Implementations are targeted; and
(iii) sublicense a MIPS Open CERTIFIED Independent Core Implementation to another person or entity that is legally authorized to enter into this Agreement, and that has entered into and provided an executed copy of this Agreement to MIPS.
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(d) Prohibition Against Exceeding License. You are not licensed to, and You agree not to, (I) exceed the scope of the licenses granted in this Agreement, or (II) license (whether proprietary or open source), disclose or otherwise provide any cores developed hereunder or any MIPS Open Core Deliverables licensed hereunder to third parties including Your affiliates, or otherwise use the MIPS Open Core, MIPS Open Core Deliverables or MIPS Open Core IP Rights, except in strict compliance with this Agreement or as expressly and separately authorized in writing by MIPS. Without limiting the foregoing, you may not license the MIPS Open Core under any third party open source license, or combine the MIPS Open Core with any third party open source code or other items in any manner or take any other action that would subject the MIPS Open Core to any third party open source software terms and conditions.
(e) No Modification of MIPS Open Core. You are not licensed to, and You agree not to, subset, superset or in any way modify, augment or enhance the MIPS Open Core. Entering into the MIPS Open Architecture Agreement, or another license from MIPS or its affiliate, does NOT affect the prohibition set forth in the previous sentence.
(f) Third Party IP. You acknowledge that third party hardware, software, tools, or other intellectual property (“Third Party IP”) may be identified among the MIPS Open Core Deliverables and may be required to implement the MIPS Open Core and provide a MIPS Open CERTIFIED Independent Core Implementation. You shall be responsible for obtaining all permissions, licenses, and consents necessary for to use any Third Party IP and following the license or providing attributions applicable to Third Party IP.
4. No Implied Rights; Limitations: The license under this Agreement is granted solely by MIPS Tech, LLC, and is only granted to You (and not to third parties including Your affiliates). You are not licensed under this Agreement to (a) any MIPS Direct-Licensed Cores (or any other cores except the MIPS Open Core), (b) any MIPS Architecture (including without limitation Releases 1 through and including 6 of the MIPS Architecture), or (c) modify or in any way include under the scope of this Agreement any MIPS Direct-Licensed Core or any other core or architecture licensed separately to You or Your affiliate by MIPS or a third party. This Agreement does not apply to or affect any products or technologies You or Your affiliates licensed or purchased separately from MIPS or its affiliates, and this Agreement does not amend, supplement or substitute the terms of other agreements between MIPS or its affiliates, and You or Your affiliates. You do not receive any rights hereunder, expressly, by implication, estoppel or otherwise other than the rights expressly granted in this Agreement.
5. MIPS Ownership: MIPS retains all ownership in and to the “MIPS Open Architecture” described in the MIPS Open Architecture Agreement, all other MIPS Architectures, the MIPS Open Core, MIPS Open Core IP Rights, MIPS Open Core Deliverables, MIPS Direct-Licensed Cores and all intellectual property rights therein (collectively, “MIPS Technology”). You retain Your ownership in Your products developed, manufactured and sold or distributed by You subject to MIPS’ underlying ownership rights described in the previous sentence. You may, but are not required to, provide suggestions, proposal, ideas, recommendations or other feedback, in any form (“Feedback”), to MIPS. To the extent You elect to provide any Feedback to MIPS, You hereby grant to MIPS a perpetual, irrevocable, royalty-free, fully-paid, sublicensable, transferable, non-exclusive, worldwide right and license to make, have made, use, sell, offer for sale, import, export, distribute, modify, create derivative works of, disclose and otherwise exploit such Feedback in any manner without restriction.
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10. Limitation of Liability: TO THE FULLEST EXTENT NOT PROHIBITED UNDER APPLICABLE LAW, IN NO EVENT SHALL MIPS OR ANY OF ITS AFFILIATES BE LIABLE FOR ANY DAMAGES, LOSSES OR OTHER LIABILITY, INCLUDING BUT NOT LIMITED TO ANY DIRECT, CONSEQUENTIAL, INDIRECT, STATUTORY, PUNITIVE, EXEMPLARY OR SPECIAL DAMAGES OR LOSSES AND ANY DAMAGES OR LOSSES FROM LOST PROFITS OR REVENUES, AND WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM OR IN CONNECTION WITH THIS AGREEMENT OR YOUR PERFORMANCE UNDER THE AGREEMENT, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
11. Term and Termination: The term of this Agreement shall begin on the Effective Date and continue unless terminated as provided in this Agreement (“Term”). If You breach this Agreement and fail to remedy such breach within thirty (30) days after written notice from MIPS, this Agreement shall automatically terminate. Sections 2, and 4 through 14 inclusive, of this Agreement shall survive termination, and MIPS reserves its rights and remedies in the event of termination.
12. MIPS Open Core Development Covenants:
(a) To preserve MIPS’ ability to continue to update, enhance, develop and commercialize the MIPS Technology, You hereby perpetually and irrevocably (both during and after the Term) agrees that You and Your affiliates will not enforce or assert or authorize or assist any third party (including any affiliate) any MIPS Blocking Patents in connection with, or in a manner which in any way limits, hampers or prevents, the use, design, development, modification, enhancement, testing, copying, and licensing or other distribution, by MIPS, its distributors, resellers, OEMs, agents, affiliates, customers, tools vendors, licensees (through multiple tiers of licensing and sublicensing) or end users in any country (“MIPS Community Members”), of the MIPS Open Core, MIPS Direct-Licensed Cores, any MIPS Architecture and other MIPS Technology, tools, physical implementations of MIPS core designs and MIPS Architectures, and (ii) other products incorporating or using MIPS Technology. “MIPS Blocking Patents” means all claims contained in patents or patent applications owned by, licensed to or assigned to You or Your affiliates, which cover or are necessary to implement any MIPS Technology.
(b) If You or Your affiliates, agents, representatives or assignees file, threaten to or bring a claim against, or voluntarily participate in or induce a third party to seek to invalidate, any patent or other intellectual property right of MIPS or its affiliate related to any MIPS Products, either unmodified or as incorporated into products, technology or tools of a MIPS Community Member (any of the foregoing, a “MIPS Adverse Claim”), then Your rights and licenses under this Agreement shall immediately and automatically terminate and You shall reimburse MIPS for its attorneys’ fees and costs incurred in connection with its defense against such MIPS Adverse Claim.
13. General: By entering into this Agreement, You give permission to MIPS and its affiliates to identify You as an Entity participating in a MIPS Open program for the MIPS Open Core in MIPS publications and/or websites. If MIPS updates this Agreement by publishing such update on the MIPS Open website, any subsequent download of MIPS Open Core Deliverables from the MIPS Open website following such publication shall be governed by the updated Agreement. This Agreement contains the entire agreement between the parties concerning the matters contained herein and supersedes any prior or contemporaneous discussions or representations of any party. This Agreement may not be modified expect by a writing duly executed by both parties. This Agreement is governed by the laws of the State of California, USA without reference to conflicts of law principles. You hereby expressly consent to the personal jurisdiction of the state and federal courts located in Santa Clara County, California USA for any disputes arising from or related to this Agreement. You may not assign, transfer or delegate any rights under this Agreement (including by operation of law, merger, consolidation or change of control) without MIPS’ prior written consent and any such attempted transfer shall be null and void. Subject to the foregoing, this Agreement shall be binding upon and shall inure to the benefit of the parties to this Agreement and their permitted successors and assigns.
14. U.S. Government Rights – Commercial Software: Any licensee or sublicensee under this Agreement that is a government user is subject to MIPS’ standard license agreement and applicable provisions of FAR and its supplements. If You or Your authorized sublicensee is permitted hereunder to provide any software, documentation, and/or related items and technology provided hereunder to any agency of the U.S. or of any state or local government, You will include this provision in any agreement governing the provision of such items.
Exhibit A
MIPS Open Core–Compatibility Verification Process 1. You must verify each MIPS Open Independent Core Implementation developed by You under the Agreement for the MIPS Open Core that You have licensed under such Agreement, on each manufacturing process to be used for volume manufacture. For each such MIPS Open Independent Core Implementation developed pursuant to the Agreement, You shall run the verification test suite (“VTS” or “Verification Test Suite”) provided under this Agreement by MIPS without any modification to the VTS, in accordance with the process set forth herein.
2. Verification Process
(a) For each MIPS Open Independent Core Implementation developed pursuant to the rights granted under the Agreement, You shall run the VTS on the final production version of the layout netlist for such MIPS Open Independent Core Implementation (“Final Netlist”), instantiated within a test bench provided by MIPS (the “Verification Test Bench”). The Final Netlist instantiated within the Verification Test Bench, as applicable, is referred to herein as the “Netlist Verification Environment.” You shall deliver to MIPS a copy of the log resulting from running the VTS on the Netlist Verification Environment and any other resulting data (“Netlist Log Results”).
(b) In addition to the Netlist Log Results delivered pursuant to Section 2(a), You shall provide MIPS with a copy of the Netlist Verification Environment and any other data required for MIPS to recreate the running of the VTS on the Netlist Verification Environment (collectively, the “Netlist Test Deliverables”).
(c) Within thirty (30) days of MIPS’ receipt of the Netlist Test Deliverables, MIPS shall review the Netlist Log Results, and, at its option, may run the applicable VTS on the Netlist Verification Environment delivered by You and may notify You in writing that the MIPS Open Independent Core Implementation has passed the compatibility verification process, or that the MIPS Open Independent Core Implementation has not passed together with details of the failure. In the event that MIPS does not provide such written notification to You within such thirty (30) day period, the MIPS Open Independent Core Implementation will be deemed to have passed the compatibility verification process. MIPS will give notice that a MIPS Open Independent Core Implementation has passed only when the Netlist Log Results and MIPS’ log results (if any) indicate that no errors have been detected or MIPS agrees to waive any errors detected.
3. You shall perform Your normal and reasonable test procedure consistent with the VTS, for chips or other product You develop in accordance with the Agreement (“Normal Licensee Test Procedure”). You will notify MIPS of the details of the Normal Licensee Test Procedure and will reasonably consider comments from MIPS about such procedure.
4. The VTS and Netlist Verification Environment, and any portion or derivative thereof, may not be used to test or verify core designs other than MIPS Open Independent Core Implementations developed strictly in accordance with, and expressly authorized under, this Agreement. You are not licensed to use or access the VTS or Netlist Verification Environment for any other purpose.
