Ну я не знаю. Вроде как 32 битные чипы они перестали делать в конце 90, а чипы типа R14K - это для серверных платформ. А чипы на базе ядра mips 4k - это не оригинальный мипс, а кастрированные варианты, в некоторых даже нет внешней шины памяти.
MIPS намного мощнее, но пока по параметру производительность/цена проигрывал х86 Планируют выпуск следующего поколения мипсов, с 4 и8 ядрами вот они то и будут конкурировать на серваках.. ну и на десктопах теперь с АРМмами..
Для мобильных девайсов наверно АРМ и их SoC для серваков и мощьных рабочих станций - MIPS
берем старый затюканый и выпускаемый (sic !) 79RC32334
Programmable I/O (PIO)
◆
– Input/Output/Interrupt source
RC32300 32-bit Microprocessor
◆
– Individually programmable
– Up to 150 MHz operation
◆ SDRAM Controller (32-bit memory only)
– Enhanced MIPS-II Instruction Set Architecture (ISA)
– Cache prefetch instruction – 4 banks, non-interleaved
– Conditional move instruction – Up to 512MB total SDRAM memory supported
– DSP instructions – Implements full, direct control of discrete, SODIMM, or DIMM
– Supports big or little endian operation memories
– MMU with 32 page TLB – Supports 16Mb through 512Mb SDRAM device depths
– 8kB Instruction Cache, 2-way set associative – Automatic refresh generation
– 2kB Data Cache, 2-way set associative ◆ Serial Peripheral Interface (SPI) master mode interface
– Cache locking per line
UART Interface
◆
– Programmable on a page basis to implement a write-through
– Two 16550 compatible UARTs
no write allocate, write-through write allocate, or write-back
– Baud rate support up to 1.5 Mb/s
algorithms for cache management
– Modem control signals available on one channel
– Compatible with a wide variety of operating systems
Memory & Peripheral Controller
◆
◆ Local Bus Interface
– 6 banks, up to 64MB per bank
– Up to 75 MHz operation
– Supports 8-,16-, and 32-bit interfaces
– 26-bit address bus
– Supports Flash ROM, SRAM, dual-port memory, and
– 32-bit data bus
peripheral devices
– Direct control of local memory and peripherals
– Supports external wait-state generation
– Programmable system watch-dog timers
– 8-bit boot PROM support
– Big or little endian support
– Flexible I/O timing protocols
Process 65nm GP
Frequency >1.11 GHz (worst case)
Performance 2.0 DMIPS/MHz
Power 0.65 mW/MHz
Core area 1.7mm2 (core only, fully placed and routed)
Total die area 2.5mm2 (includes core plus caches)
The 65nm Loongson 3 (Godson-3) is able to run at a clock speed between 1.0 to 1.2 GHz, with 4 CPU cores (10W) first and 8 cores later (20W), and it is expected to debut in 2010. [8] The first version of the chip will only support DDR2 DRAM...the -march=loongson2f and -mtune=loongson2f flags can be used to enable those optimizations.